Recently, a WL-CSP (Wafer Level-Chip Size Package) which realizes downsizing, higher functionality, and higher performance of semiconductor devices has been put to practical use. Concerning the WL-CSP, the packaging process is completed in the wafer state, and individual chip sizes cut out by dicing become package sizes.
That is, in the manufacturing processes for a semiconductor device employing the WL-CSP, on the surface of a wafer in which a plurality of semiconductor chips are formed, a polyimide layer and rewiring are formed, and thereafter, a front side resin layer for sealing these is formed. After external terminals are formed on the front side resin layer, semiconductor devices of a WL-CSP having the same package size as that of the semiconductor chip are obtained by cutting (dicing) the wafer together with a passivation film and the sealing resin along dicing lines set between the respective semiconductor chips.    Patent document 1: Japanese Unexamined Patent Publication No. 2003-60119    Patent document 2: Japanese Unexamined Patent Publication No. 2004-336020